Design Rule Verification Report
Date:
1/10/2021
Time:
6:03:56 PM
Elapsed Time:
00:00:02
Filename:
C:\Users\Public\Documents\Altium\Battery Monitoring System (V4)\BMS.PcbDoc
Warnings:
0
Rule Violations:
4
Summary
Warnings
Count
Total
0
Rule Violations
Count
Clearance Constraint (Gap=0.127mm) (All),(All)
0
Short-Circuit Constraint (Allowed=No) (All),(All)
0
Un-Routed Net Constraint ( (All) )
0
Modified Polygon (Allow modified: No), (Allow shelved: No)
0
Width Constraint (Min=0.127mm) (Max=25.4mm) (Preferred=0.254mm) (All)
0
Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (InPadClass('PowerPads'))
0
Power Plane Connect Rule(Relief Connect )(Expansion=0.3mm) (Conductor Width=0.127mm) (Air Gap=0.127mm) (Entries=4) (All)
0
Minimum Annular Ring (Minimum=0.076mm) (All)
0
Hole Size Constraint (Min=0.3mm) (Max=6.3mm) (All)
0
Hole To Hole Clearance (Gap=0.25mm) (All),(All)
0
Minimum Solder Mask Sliver (Gap=0mm) (All),(All)
0
Silk To Solder Mask (Clearance=0.127mm) (IsPad),(All)
0
Silk to Silk (Clearance=0mm) (All),(All)
0
Net Antennae (Tolerance=0mm) (All)
0
Board Clearance Constraint (Gap=0mm) (All)
4
Height Constraint (Min=0mm) (Max=1816.048mm) (Prefered=12.7mm) (All)
0
Total
4
Board Clearance Constraint (Gap=0mm) (All)
Board Outline Clearance(Outline Edge): (Collision < 0.2mm) Between Board Edge And Track (0mm,0mm)(0mm,60mm) on Top Layer
Board Outline Clearance(Outline Edge): (Collision < 0.2mm) Between Board Edge And Track (0mm,0mm)(75mm,0mm) on Top Layer
Board Outline Clearance(Outline Edge): (Collision < 0.2mm) Between Board Edge And Track (0mm,60mm)(75mm,60mm) on Top Layer
Board Outline Clearance(Outline Edge): (Collision < 0.2mm) Between Board Edge And Track (75mm,0mm)(75mm,60mm) on Top Layer
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